1. Field of the Invention
The present invention relates to a ferroelectric memory, and particularly, to a ferroelectric memory that includes a ferroelectric capacitor and a bit line.
2. Description of the Related Art
The ferroelectric capacitors have a nonvolatile feature as well as a high-speed data reading and writing feature. Therefore, the ferroelectric capacitors are put into practical use as ferroelectric memories (FeRAMs) by taking advantage of these features. The ferroelectric memories can exercise the nonvolatile feature at a high speed and with low power consumption in the same manner as SRAMs do, so that the ferroelectric memories are utilized for LSIs for IC cards and tag chips, and are widely used in the market.
The readout of the potential of a cell of the ferroelectric memory is determined depending on the capacitance ratio of the cell to a bit line, as in DRAMs. When the capacitance is small, the memory area is decreased and the capacitance of the bit line lowers, so that the voltage applied to the ferroelectric capacitor of the cell lowers. Therefore, the charge supplied from the ferroelectric capacitor to the bit line reduces, and thereby the readout margin of a sense amplifier reduces. On the contrary, a devisal is conceivable in which a load is applied to the bit line to thereby prevent the reduction of voltage applied to the ferroelectric capacitor of the cell.
Further, since the capacitance to be added to the bit line is required to correspond to that of the ferroelectric capacitor of the cell, it is presumable that a great amount of gate capacitance or source-drain capacitance, or a ferroelectric capacitor or the like be utilized. However, the gate capacitance and the source-drain capacitance have a problem of increasing area, and the ferroelectric capacitor has a problem of insufficient accuracy in fluctuation.
Further, the ferroelectric memories are disclosed in Japanese Patent Application Laid-Open No. 2001-319472 (Patent Document 1) and Japanese Patent Application Laid-Open No. 2004-13951 (Patent Document 2).